Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by using predetermined logic blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. One aspect of such a customizable integrated circuit design is referred to as RRAM.
RRAM (Reconfigurable RAM) contains sets of memories of the same type that are placed compactly within a memory matrix. An RRAM, as the term is used herein, is a megacell that can be considered as a set of memories with built-in self testing and built-in self correction. RRAM also contains sets of embedded tools that are used for mapping arbitrary logical customer memory designs to the physical memories in the matrix.
Each RRAM design typically contains several RRAMs. At the stage of memory placement during the design process, memories of the customer's netlist are mapped to the customizable standardized memories of the RRAMs. Then the RRAM megacells are configured in accordance with the resulting memory mapping. The configured RRAM is called a tiling netlist. If the RRAM contains partially configured memories, high performance tiling of the RRAM is problematic.
What is needed, therefore, is an efficient method for tiling any arbitrary customer memory into a group of basic memories when the customer memories contain partially configured memories without unduly increasing the size of the configuration matrix.